A New Approach for Nonlinearity Test of High Speed DAC Chun Wei Lin, Sheng Feng Lin, Shih Fen Luo Department of Electronic Engineering, National Yunlin University of Science & Technology Douliou, Yunlin, Taiwan Abstract  In this work, we propose a novel test scheme for high speed digitaltoanalog converter (DAC) based on under sampling technique. The undersampling technique is constructed by a pulsewidthmodulation (PWM) modulator. The DAC output signal is modulated through a low frequency sinusoidal carrier and converted to low speed pulse signal. The pulse width of low speed pulse signal can be measured using conventional logic analyzer and the nonlinearity error of DAC can be estimated by analyzing the variation of pulse width. An experiment on 8bits 50~300MS/s DAC has shown very good result and only requires a set of instruments which have sample rate lower than that of the circuitundertest (CUT). Index Terms  digitaltoanalog converter, undersampling technique, pulsewidthmodulation (PWM), sinusoidal carrier.
I. INTRODUCTION In the past few years, along with advance in consuming electronics and communication technologies, high speed DACs were applied to many applications. Conventional DAC test methods require instruments with higher speed than a CUT to sample and characterize the performance of the circuit accurately [1]. However, the bandwidth limitation of transferring channel from chip to instruments will result in more distortion. Therefore, on chip testing method was proposed to obtain accurate test result for high speed DAC [2][5][6]. In addition, the signal under test can be converted into specific test signature for convenience of analysis. By transferring amplitude value to the representation of duty ratio or frequency of pulse signal, a digital counter can be used to measure analog signal [3][4][7]. However, these techniques need high speed onchip processing circuit, which may increase design effort and raise another test issue on these circuits. In this work, we develop a DAC test scheme based on undersampling technique. The analog signal of DAC is converted into pulse stream and the relationship between nonlinearity of DAC and width of pulse stream can be derived. Under this method, we can use logic analyzer to estimate
nonlinearity of DAC and it will enhance the capability of automatictest equipment (ATE) on testing high speed DAC. II. UNDERSAMPLING TECHNIQUE The critical problem of test high speed DAC is the need of instruments with higher operational frequency than CUT. For this reason, we ought to measure signal in several periods instead of in single period. The fundamental concept of this work is shown in Fig.1. Assume f ( ω t ) is the output waveform of DAC with period T . Three sample nodes, p1 to p3 , are captured in three periods respectively. If we define the voltage and time difference of two sample node are ∆Vi and Wi , then ∆Vi can be transferred to be a function of ∆Wi , where ∆Wi = Wi − T . Therefore, the nonlinearity error of CUT, f ( ω t ) / dt , will be represented as the variation of pulse width, i.e. ∆Wi . To accomplish undersampling technique as mentioned above, we propose an implement scheme based on a PWM structure which is shown in Fig. 2. The signal under test and carrier, f ( ω t ) and f (ω ' t ) , are fed into comparator and converted to timing signature w(t ) . Since this timing signature can be treated as a digitized signal, we can use conventional instrument to observe this signal instead of capturing high speed analog signal. Moreover, due to Wi correspond to difference voltage of two sampled points, the offset effect of comparator will be cancelled naturally.
f (ω t )
∆V1 p1
T
∆V2
p3
p2
∆W1 W2
W1 Fig. 1. Fundamental concept of undersampling technique.
1424423965/08/$20.00 ©2008 IEEE
Lowpass filter
DAC
f (ω t ) Vda Comparator
Carrier generotor
s(t )
w(t )
f (ω ' t )
f (ω t )
Vc
−Vda
f (ω ' t )
−Vc ∆T
Tda Wi
s(t ) w (t)
Tc (a)
Wi = T + ∆Wi
Fig. 2. PWM implement structure for undersampling technique.
z
III. THEORETICAL DEVELOPMENT x
A. Using triangular carrier As in the previous section, we know that the nonlinearity error of CUT is modulated to variation of pulse width signature. To develop analysis method of signature, we assume the carrier signal is triangular wave firstly as shown in Fig. 3(a). The amplitude and period of carrier and output signal of CUT is ( Vc , Tc ) and ( Vda , Tda ) respectively. We enlarge the shadow area in Fig. 3(a) and shown in Fig. 3(b). In Fig. 3(b), the slope of carrier and output signal of CUT can be expressed as: mda _ i =
1+
∆T . mda _ i mc
i =1
N
N
≈ Tda +
and mda = mda _ i (ideal ) =
∆T m 1 + da mc
Vda . Tda / 4
Therefore, the operation frequency f c of carrier will be: fc =
∆w
1 Tda + ∆T
and ∆T <
Tda m (1 + da ) . 2N mc
fault free faulty carrier
y
Fig. 3. (a) Triangular carrier of undersampling technique. (b) Shadow area in (a). (c) With faulty case.
With the faulty case shown in Fig. 3(c), a nonlinearity error in output signal of CUT is corresponded to a change of sampling position ∆w . The slope of faulty signal can be represented as:
mf =
zf x + ∆w
=
∆T − (W f − Tda ) ∆T − ( x + ∆w) mc = mc . (2) x + ∆w W f − Tda
, where W f is pulse width of modulated signal in faulty case. In consequence, we can estimate slope of faulty signal from derived relationship through adoption of adequate carrier signal and measurement of faulty pulse width.
N
ΣΤ = Tda ( N + 0.5) > ¦ Wi = NW
¦ Wi
zf
(c)
If N sample points are required, we have to spend ( N + 0.5) cycles to obtain signatures Wi , where i = 1,2,.., N . So, we need to define the operation frequency of carrier meet this requirement. For this problem, we start with the inequality correlated to total sample time ΣΤ .
i =1
z
x
Thus, we can find the pulse width of modulated signal will be:
, where W =
(b)
V z z and mc = = c . x y Tc / 4
Wi = Tda + x = Tda +
y
(1)
B. Using sinusoidal carrier In a practical test environment, generate a precise sinusoidal wave is more easy than a triangular wave. But using sinusoidal wave as carrier signal is not an intuitive linear modulation. To revise the derived equations above, we have to regard sinusoidal carrier as combination of many linear pieces. This piecewise linear concept is reasonable since there should be quite a great deal of sample points and the correlation between adjacent points can be took as a linear relationship. Hence, (1)
be counted into average when calculating m f 1 and the DNL estimation should be revised to be:
can be modified to be: ∆T <
Tda N
2×¦
i =1
1 m (1 + da ) m c [i ]
mf1 =
, and d [Vc sin( m c [i ] =
2πt )] 2πVc Tda + ∆T 2πt cos( ) = dt Tda + ∆T Tda + ∆T t =t
2−
i ( t2 − t1 ) N +1
, where i = 1,2,..., N , t1 =
Tda + ∆T V T + ∆T −V sin −1 ( da ) and t2 = da sin −1 ( da ) . 2π 2π Vc Vc
Similarly, (2) can be modified to be: mf =
∆T − (W f [i ] − Tda ) W f [i ] − Tda
m1 + m 2 + m 3 3
mc [i ] , where i = 1,2,..., N .
In the previous section, we have derived the relationship between slope of DAC output signal and pulse width of modulated signal. To reduce estimated errors, we can directly increase the number of sample points. This mechanism can be performed easily by adjusting the operation frequency of carrier signal. For example, a case of 8bits DAC with 255 quantization levels may needs 1020 sample points, i.e. 4 sample points per quantization level. After that, we need to extract 255 signatures from 1020 samples. If we consider an ideal case as shown in Fig. 4(a) that DAC is ideal and all sample points are distributed uniformly. In this case, the slope to be estimated, m f , can be take account average value of slop between adjacent points, mi where i = 1,..,4 . Nevertheless, the quantization level of DAC is not ideal and sample points are not distributed uniformly which as shown in Fig. 4(b). In this situation, the slope of section crosses transition edge of quantization level, i.e. m4 between the third and fourth sample point, should be took account into average when calculating both m f 1 and m f 2 . Consequently, the differential nonlinearity (DNL) can be estimated through the following equations: m1 + m2 + m3 + m4 4 , where m5 > m3 > m4 .
m4 + m5 + m6 + m7 + m8 5
, when m5 > m 4 > m3 . To explain the DNL estimation, we assume N sample points are captured and the slopes between adjacent points are distributed in Fig. 5. The first step is finds all local max. value in Fig. 5 and then calculates average value among these maximum points with respect to their faulty situations we stated in previous section. For instance, because of m 5 j > m3 j > m 4 j then m f 1 j = (m1 j + m 2 j + m3 j + m 4 j ) 4 and m f 5 j = (m 4 j + m5 j + m6 j + m 7 j + m8 j ) 5 . For another situation, m 5 k > m 4 k > m 3 k , they will be m f 1k = ( m 1k + m 2 k + m 3k ) 3 and m f 5k = (m 4 k + m5k + m6 k + m7 k + m8 k ) 5 .
IV. NONLINEARITY ESTIMATION
mf1 =
and m f 2 =
and m f 2 =
m4 + m5 + m6 + m7 + m8 5
Furthermore, we need to consider another condition that will cause an error in estimating nonlinearity of CUT. With the condition of m5 > m4 > m3 in Fig. 4(b), that means the third sample point is very close to transition edge of quantization level. In other words, there exists a great deal of difference between calculated slope m4 and actual slope between the third sample point and transition edge. Therefore, m4 can’t
m3 m2
m4
mf
m1
ideal filtering real filtering
(a)
m8 m7 m6
m5
m1
m2
mf2
m4
m3
mf1
ideal filtering real filtering
(b) Fig. 4. (a) Representation of 4 sample points per quantization level in ideal case. (b) Representation of 4 sample points per quantization level in faulty case. local max . slope points
mi
m2 j
m5 j m6 j m7 j
m1 j m3 j
m4 j
m8 j
m2 k m1k
m5 k m6 k m4 k
m 3k
m7 k m8k i
Fig. 5. Distribution of slope between adjacent sample points.
Hence, for nbits DAC with N sample points, we formalize the algorithm of DNL estimation to be: for ( mi ; i=1 to N) find local maximum set mmax [k ] ={ mmk }, k=1,2,…, 2 n − 1
for (k=1 to 2 n − 1 ) case ( mmk +1 > mmk +1 − 2 > mmk +1 −1 ) mk +1 −1
¦ mj
DNL[k]=
j = mk −1
mk +1 − mk + 1
case ( mmk +1 > mmk +1 −1 > mmk +1 − 2 ) mk +1 − 2
¦ mj
DNL[k]=
j = mk −1
mk +1 − mk
The integral nonlinearity (INL) generally can be calculated from DNL and expressed to be:
V.
EXPERIMENT RESULT
In this section, an 8bits 200MS/s DAC are applied by the proposed method to demonstrate the nonlinearity estimation. The DAC was enabled to output triangular wave with normalized amplitude Vda and period Tda , and the carrier signal for PWM modulation is decided to be f (ω ' t ) = 1.155 × Vda sin( 2πt ((5ns × 255 × 2) + (5ns × 0.415))) . In this case, we extract 255 signatures from 1020 captured samples by the method we mentioned in previous section. Fig. 6(a)(b) shows the estimated result with the real one. It is seen that the estimated nonlinearity match well with the real one. The maximum estimated error of DNL and INL are 0.18LSB and 0.35LSB respectively. In addition, we also evaluate the RMS error of estimation with respect to operation frequency of CUT and measurement resolution of modulated signal’s pulse width. Fig. 6(c) shows the RMS error of estimated result. For 300MS/s CUT with 400ps measurement resolution, the RMS error is under 0.15LSB. This means that for this method, nonlinearity of high speed DAC can be estimated accurately by using conventional logic analyzer such as Agilent16900 series.
i
INLestimation [i ] = ¦ DNL[k ] . k =1
Using this simple expression for INL estimation is intuitive but also lead error in calculation. A little bit of systematic error in DNL estimation will be integrated into an unbelievable error. To resolve this problem, we attempt to trace the source of error and distinguish real INL value from it. In our proposed scheme, the systematic error is brought from the PWM process inherently. This is because the sinusoidal carrier using in PWM is treated to be combination of many linear pieces when developing the estimation method of DNL. Thus, there exists a little error between the estimated DNL and real DNL. In addition, the variation of this error is periodic since it appears cyclically with respect to frequency of DAC output signal. For this reason, the estimated INL should be characterized to be: i
i
k =1
k =1
i
k =1
k =1
INL [ i ] = HPF { ¦ [ DNL real [ k ] + ε (ω k )]} = ¦ DNL real [ k ] .
(a)
!
$
i
INL estimation [ i ] = ¦ DNL estimation = ¦ [ DNL real [ k ] + ε (ω k )]
, where ε (ωk ) is systematic error in DNL and ω = 2π Tda . From the signal point of view, we can regard INL as a signal which composed of integration of DNL and systematic error signal. Because period of DAC output signal is quite a large value, we know that the frequency of systematic error is far less than DNL signal. Consequently, we can remove systematic error and yield more accurate INL estimation simply by using a high pass filter (HPF) which modifies the INL estimation to be:
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(b) Fig. 6. (a) DNL estimated result of an 8bits 200MS/s DAC. (b) INL estimated result of an 8bits 200MS/s DAC.
RMS error (LSB) 0.6 0.5 0.4 0.3 0.2 0.1 0 300 250
700 600
200 Operation frequency (Ms/s)
500 400
150
300 100
200 50
100
Measurement resolution(ps)
0
(c) Fig. 6. (c) RMS error of DNL estimation with respect to operation frequency and meas. resolution.
VI. CONCLUSION In this paper, we have proposed a method for estimating the nonlinearity of high speed DAC. The method is based on an undersampling technique implemented by a PWM modulator. The nonlinearity error of CUT is converted to be variation of pulse width. The conversion relationship is derived and has been verified. The experiments of 8bits 50~300MS/s DAC show very good results and demonstrate the practicability. One merit of the method is that it doesn’t need high speed or high resolution equipments to capture analog signal. In addition, it is suitable for developing digitized builtin selftest scheme. ACKNOWLEDGEMENT The authors would like to thank National Chip Implementation Center (CIC) for technical support and chip fabrication. REFERENCE [1] J.L. Huertas, Test and DesignforTestability in MixedSignal Integrated Circuits, Kluwer Academic Publishers, 2004. [2] K. Arabi, B. Kaminska, M. Sawan,” On Chip Testing Data Converters Using Static Parameters,” IEEE Trans. on VLSI System, Vol. 6, No. 3, pp. 409418, 1998. [3] J.L. Huang, C.K. Ong, K.T. Cheng,” A BIST Scheme for OnChip ADC and DAC Testing,” Proc. IEEE Design Automation & Test in Europe, pp. 216220, 2000. [4] G. X. Chen, C.L. Lee, J.E. Chen,” A New BIST Scheme Based on a SummingintoTiming Signal Principle with Self Calibration for the DAC,” Proc. IEEE Asia Test Symp., pp. 5861, 2004. [5] S. Rafeeque K.P., V. Vasudevan,” A BuiltinSelfTest Scheme for Segmented and Binary Weighted DACs,” J. of Electronic Testing, Theory &Appl., Vol. 20, No. 6, pp. 623638, Dec. 2004. [6] V. Kerzerho et al,” A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in complex SiPs,” IEEE Design & Test of Computers, Vol.23, Issue 23, pp. 234243, 2006. [7] S.J Chang, C.L. Lee, J.E. Chen,” BIST Scheme for DAC Testing,” Electronic Letters, Vol. 38, No. 15, pp. 776777, July 2002.